Recently, a polymetal gate structure of a semiconductor device, particularly, a DRAM (Dynamic Random Access memory) has been widely used, in order to improve the operation speed of the device.
The polymetal gate structure is a gate electrode structure having a metal layer laminated on a polysilicon layer. The polymetal gate structure is known to decrease resistance (sheet resistance) of a word line in a plane direction more than a polycide gate structure that is used conventionally. However, when a metal layer (for example, tungsten (W)) is directly formed on the polysilicon layer, the polysilicon layer reacts with the metal layer in a subsequent high-temperature thermal annealing, thereby forming a thick silicide layer (such as a tungsten silicide (WSi) layer) between the polysilicon layer and the metal layer. Since the silicide layer has relatively high electric resistance, formation of the silicide layer needs to be suppressed, in order for a high-speed the operation of the device. To solve this problem, Japanese Patent Application Laid-Open No. H11-233451 discloses a technique of suppressing reaction between the polysilicon layer and the metal layer, by forming a metal nitride layer such as tungsten nitride (WN) between the polysilicon layer and the metal layer.
However, when the metal nitride layer is directly formed on the polysilicon layer, the polysilicon layer reacts with the metal nitride layer in the subsequent thermal annealing, thereby forming a metal silicide nitride layer. The metal silicide nitride layer has high resistance, depending on composition or a structure of the laminated film. When the metal silicide nitride layer has a large film thickness, a low-resistance polymetal gate electrode cannot be obtained.
The inventor of the present invention proposes a method of suppressing the reaction between the polysilicon layer and the metal nitride layer, by inserting a thin silicide layer between the polysilicon layer and the metal nitride layer, in Japanese Patent Application Laid-Open No. 2003-163348.
On the other hand, in order to increase the performance of a device and to decrease the driving voltage of the device, a dual gate structure is also used. The dual gate structure uses a gate electrode containing N-type polysilicon, having N-type impurity (such as phosphorus) introduced in the gate electrode, for an N-channel transistor, and uses a gate electrode containing P-type polysilicon, having P-type impurity (such as boron) introduced in the gate electrode, for a P-channel transistor.
However, as described in Japanese Patent Application Laid-Open No. 2003-163348, when an electrode of a polymetal gate structure having a lamination of a polysilicon layer, a silicide layer, a metal nitride layer, and a metal layer is applied to the dual gate structure, the following problem occurs. Before gate patterning is performed, the N-type polysilicon layer and the P-type polysilicon layer form an adjacently-connected continuous film. A silicide layer is formed on an entire top surface of this film. Therefore, due to the thermal annealing and the like before the gate patterning, N-type impurity in the N-type polysilicon layer and P-type impurity in the P-type polysilicon layer are absorbed in the silicide layer, and are mutually diffused, thereby increasing the interface resistance and increasing a gate conversion film thickness. Therefore, the inventor of the present invention has proposed a method of preventing the mutual diffusion of impurities in the N-type and the P-type polysilicon layers via the silicide layer, by forming the silicide layer discontinuously on the P-type polysilicon layer.
However, it has become clear that when the silicide layer is formed discontinuously on the P-type polysilicon layer, sufficiently low sheet resistance cannot be obtained in the P-type polymetal gate electrode, in some cases.